High Level Synthesis Tools-an Overview from Model to Implementation
نویسنده
چکیده
The design community has to switch over from Register Transfer Level (RTL) to higher abstraction level to design a digital circuit since the design complexity of digital circuits and System on Chip (SoC) are swelling. This increasing complexity and recent advancement in on-chip circuit has paved the way for High Level Synthesis (HLS) improvement (precisely for FPGA). The commercial HLS in earlier stage were unsuccessful due to may reason, however the recent HLS tools are developed to support in various means, such as, covering maximum language, modeling the design based on the platform, an enhancement in the algorithm, targeting domain-specific and technology-based implementation. The approach to select the HLS tool among the various tools available based on result quality (i.e. QoR), capabilities and usability are assessed in this paper. The industries are accepting the HLS tools in their design flow since the tools are progressing steadily.
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